數(shù)字硬件建模SystemVerilog-歸約運(yùn)算符（Reduction operators）

經(jīng)過幾周的更新，SV核心部分用戶自定義類型和包內(nèi)容已更新完畢，接下來就是RTL表達(dá)式和運(yùn)算符。

馬上HDLBits-SystemVerilog版本也開始準(zhǔn)備了，基本這一部分完成后就開始更新~

介紹

歸約運(yùn)算符對(duì)單個(gè)操作數(shù)的所有位執(zhí)行運(yùn)算，并返回標(biāo)量（1位）結(jié)果。表5-9列出了歸約運(yùn)算符。

表5-9：RTL建模的歸約運(yùn)算符

歸約運(yùn)算符包括一個(gè)NAND和一個(gè)NOR運(yùn)算符，這是按位運(yùn)算符所沒有的。歸約AND OR 和 XOR 運(yùn)算符一次執(zhí)行一位操作，從最右邊的位（最低有效位）向最左邊的位（最高有效位）移動(dòng)。歸約NAND、NOR和XNOR運(yùn)算符首先分別執(zhí)行歸約AND、OR或XOR運(yùn)算，然后反轉(zhuǎn)1位結(jié)果。

AND、NAND或NOR運(yùn)算符是X-optimistic。對(duì)于歸約運(yùn)算符，如果操作數(shù)中的任何位為0，結(jié)果將為1’b0。對(duì)于歸約NAND，如果操作數(shù)中的任何位為0，結(jié)果將為1’b1。類似地，對(duì)于歸約運(yùn)算符，或者如果操作數(shù)中的任何位為l，結(jié)果將為1’b1。對(duì)于歸約NOR，如果操作數(shù)中的任何位為l，結(jié)果將是1’b0.歸約XOR和XNOR運(yùn)算符是X-pessimistic。如果操作數(shù)的任何一位是X或Z，結(jié)果將是1’bx。表5-10顯示了幾個(gè)示例值的每個(gè)歸約運(yùn)算符的結(jié)果。

表5-10：歸約操作的示例結(jié)果

示例5-6說明了一個(gè)小型RTL模型，該模型利用歸約運(yùn)算符檢查數(shù)據(jù)值的正確奇偶性，圖5-6顯示了該RTL模型綜合結(jié)果。

示例5-6：使用歸約運(yùn)算符：使用異或的奇偶校驗(yàn)

//
//Book,"RTLModelingwithSystemVerilogforASICandFPGADesign"
//byStuartSutherland
//
//Paritycheckerusingevenparity,registerederrorflag
//
//Copyright2016,StuartSutherland.Allrightsreserved.
//
//Version1.0
//

//
//User-definedtypedefinitions
//
`begin_keywords"1800-2012"http://useSystemVerilog-2012keywords
packagedefinitions_pkg;
typedefstruct{
logic[7:0]data;
logicparity_bit;
}data_t;
endpackage:definitions_pkg
`end_keywords


//
//Paritycheckerusingevenparity,registerederrorflag.
//Thecombineddatavalueplusparitybitshouldalwayshave
//anevennumberofbitssetto1
//
`begin_keywords"1800-2012"http://useSystemVerilog-2012keywords
moduleparity_checker
importdefinitions_pkg::*;
(inputdata_tdata_in,//9-bitstructureinput
inputclk,//clockinput
inputrstN,//active-lowasynchronousreset
outputlogicerror//setifparityerrordetected
);
timeunit1ns/1ns;

always_ff@(posedgeclk,negedgerstN)
if(!rstN)error<=?0;
???else???????error?<=?^{data_in.parity_bit,?data_in.data};
?????//?reduction-XOR?returns?1?if?an?odd?number?of?bits?are
?????//?set?in?the?combined?data?and?parity_bit
endmodule:?parity_checker
`end_keywords

該文件的仿真文件如下：

//
//Book,"RTLModelingwithSystemVerilogforASICandFPGADesign"
//byStuartSutherland
//
//Testbench
//
//Copyright2016,StuartSutherland.Allrightsreserved.
//
//Version1.0
//
`begin_keywords"1800-2012"
moduletest
importdefinitions_pkg::*;
(outputlogicrstN,
outputdata_tdata_in,
inputlogicerror,
inputlogicclk
);
timeunit1ns/1ns;

//generatestimulus
initialbegin
$timeformat(-9,0,"ns",6);//nanoseconds,noprecision,6columns
rstN<=?0;????????????????????//?reset?DUT?(active?low)
????repeat(2)??@(negedge?clk)?;???//?hold?reset?for?2?clock?cycles
????rstN?=?1;?????????????????????//?remove?reset
????repeat?(10)?begin
??????@(negedge?clk)?;
??????data_in.data?=?$urandom();
??????data_in.parity_bit?=?$urandom()%2;??//?randomly?wrong?parity?value
??????@(negedge?clk)?check_results;
????end
????@(negedge?clk)?$finish;
??end

??//?verify?results
??task?check_results;
????$write("At?%t:?data=%b??parity_bit=%b:??",?$time,?data_in.data,?data_in.parity_bit);
????if?(^data_in.data?===?data_in.parity_bit)?begin:?good_data_in
??????$write("Good?data_in.?EXPECT:?error?=?0,?ACTUAL:?%b?",?error);
??????if?(error?===?1'b0)?$display("?OK");
??????else????????????????$display("?ERROR!");
????end:?good_data_in
????else?begin:?bad_data_in
??????$write("Bad?data_in.??EXPECT:?error?=?1,?ACTUAL:?%b?",?error);
??????if?(error?===?1'b1)?$display("?OK");
??????else????????????????$display("?ERROR!");
????end:?bad_data_in
??endtask

endmodule:?test
`end_keywords

`begin_keywords?"1800-2012"
module?top;
??timeunit?1ns/1ns;
??import?definitions_pkg::*;
??parameter?WIDTH?=?8;

??logic??clk,?rstN;
??data_t?data_in;
??logic??error;

??test???????????test?(.*);
??parity_checker?dut??(.*);

??initial?begin
????clk?<=?0;
????forever?#5?clk?=?~clk;
??end
endmodule:?top
`end_keywords

圖5-6：示例5-6的綜合結(jié)果：歸約異或（奇偶校驗(yàn)）

審核編輯：湯梓紅