2. 從模塊（SPI_slave）:

module spi_slave(

input           rst_n,

input           cs_n,

input           sclk,

input           mosi,



output          miso,

output [7:0]    reg0_out,

output [7:0]    reg1_out,

output [7:0]    reg2_out,

output [7:0]    reg3_out

);

reg miso_r;

reg [7:0] reg1_out_r;

reg [7:0] reg2_out_r;

reg [7:0] reg3_out_r;

reg [7:0] reg0_out_r;

reg start;

reg wr_rd;

reg [3:0] bit_cnt;

reg [6:0] reg_addr;

reg [7:0] reg_data;

parameter reg0_address = 7'b0000000; //address of reg0

parameter reg1_address = 7'b0000001; //address of reg1

parameter reg2_address = 7'b0000010; //address of reg2

parameter reg3_address = 7'b0000011; //address of reg3

//start

always @ (posedge sclk or negedge rst_n)

begin

if(~rst_n)

start <= 1'b0;

else

start <= 1'b1;

end

//bit_cnt

always @ (posedge sclk or negedge rst_n)

begin

if(~rst_n)

bit_cnt <= 4'b0;

else if(start)

bit_cnt <= bit_cnt + 1'b1;

end

//wr_rd

always @ (posedge sclk or negedge rst_n)

begin

if(~rst_n)

wr_rd <= 1'b0;

else if(bit_cnt == 4'b0 && mosi == 1'b0)

wr_rd <= 1'b0;

else if(bit_cnt == 4'b0 && mosi == 1'b1)

wr_rd <= 1'b1;

end

//reg_addr

always @ (negedge sclk or negedge rst_n)

begin

if(~rst_n)

reg_addr <= 7'b0;

else if(bit_cnt >= 4'd1 && bit_cnt <= 4'd7)

reg_addr <= {reg_addr[5:0],mosi};

end

//reg_data

always @ (posedge sclk or negedge rst_n)

begin

if(~rst_n)

reg_data <= 8'b0;

else if(!wr_rd && bit_cnt >= 4'd7)

reg_data <= {reg_data[6:0],mosi};

else if(wr_rd && bit_cnt == 4'd6)

reg_data <= reg2_out_r;

else if(wr_rd && bit_cnt >= 4'd7)

reg_data <= {reg_data[6:0],reg_data[7]};

end

//reg_out

assign reg0_out = reg0_out_r;

assign reg1_out = reg1_out_r;

assign reg2_out = reg2_out_r;

assign reg3_out = reg3_out_r;

always @ (negedge sclk or negedge rst_n)

begin

if(~rst_n)

begin

reg0_out_r <= 8'b0;

reg1_out_r <= 8'b0;

reg2_out_r <= 8'b0;

reg3_out_r <= 8'b0;

end

else if(!wr_rd && bit_cnt == 4'd0)

case(reg_addr)

reg0_address: reg0_out_r <= reg_data;

reg1_address: reg1_out_r <= reg_data;

reg2_address: reg2_out_r <= reg_data;

reg3_address: reg3_out_r <= reg_data;

endcase

end

//miso

assign miso = miso_r;

always @ (negedge sclk or posedge rst_n)

begin

if(~rst_n)

miso_r <= 1'b0;

else if(wr_rd && bit_cnt >= 4'd7)

miso_r <= reg_data[7];

end

endmodule

3. Testbench（tb）:

`timescale 1us/1us

module tb();

regclk_40k;

regrst_n;

reg [7:0] data_in;

regsend_start;

wiresclk;

wirecs_n;

wiremosi;

wiremiso;

wire [7:0] data_out;

wire data_out_vld;

wire [7:0] reg0_out;

wire [7:0] reg1_out;

wire [7:0] reg2_out;

wire [7:0] reg3_out;

spi_master i_spi_master(

.clk_40k          (clk_40k),     

.rst_n              (rst_n),

.data_in          (data_in),

.send_start     (send_start),

.sclk               (sclk),

.cs_n              (cs_n),

.mosi              (mosi),

.miso              (miso),

.data_out        (data_out),  

.data_out_vld (data_out_vld)

);

spi_slave i_spi_slave(

.rst_n            (rst_n),       

.cs_n             (cs_n),

.sclk             (sclk),        

.mosi            (mosi),      

.miso            (miso),      

.reg0_out      (reg0_out), 

.reg1_out      (reg1_out), 

.reg2_out      (reg2_out), 

.reg3_out      (reg3_out)

);

initial

begin

rst_n = 1'b0;

#10rst_n = 1'b1;

end

initial

begin

clk_40k = 1'b0;

forever

#1clk_40k = ~clk_40k;

end

initial

begin

send_start = 1'b0;

data_in = 8'd0;

forever

begin

    #200;

    data_in = $random()%256;

    send_start = 1'b1;

    #2

    send_start = 1'b0;

    #8000;

end

end

endmodule

4. 仿真結(jié)果:

按照testbench對(duì)SPI主從設(shè)備進(jìn)行仿真，仿真結(jié)果如圖：

1. 系統(tǒng)時(shí)鐘和SPI時(shí)鐘不一致，clk_40k為高頻系統(tǒng)時(shí)鐘，利用計(jì)數(shù)器分頻實(shí)現(xiàn)1k波特率SPI時(shí)鐘；
2. 復(fù)位信號(hào)rst_n低電平有效，正常傳輸時(shí)始終處于高電平；
3. 開始傳輸時(shí)send_start信號(hào)拉高，傳輸結(jié)束時(shí)data_out_vld信號(hào)拉高；
4. SPI主設(shè)備將輸入數(shù)據(jù)data_in并行轉(zhuǎn)mosi串行輸出，SPI從設(shè)備將接收到的串行存入數(shù)據(jù)，將移位后的數(shù)據(jù)data_out并行轉(zhuǎn)miso串行輸出。

05

SPI的優(yōu)缺點(diǎn)

5.1 SPI協(xié)議優(yōu)點(diǎn)

1. 全雙工同步串行通信；
2. 允許數(shù)據(jù)逐位傳遞；
3. 允許數(shù)據(jù)傳輸暫停；
4. 硬件結(jié)構(gòu)簡單，不需要精密時(shí)鐘；
5. 從機(jī)不需要唯一地址，也不需要收發(fā)器。

5.1 SPI協(xié)議缺點(diǎn)

1. 需要4個(gè)引腳接口；
2. 支持傳輸距離較短；
3. 硬件層面沒有定義校錯(cuò)協(xié)議和從機(jī)應(yīng)答信號(hào)。