The TPS3836, TPS3837, TPS3838 families of supervisory circuits provide circuit initialization and timing supervision, primarily for DSP and processor-based systems.

During power on, RESET is asserted when the supply voltage V_DD becomes higher than 1.1 V. Thereafter, the supervisory circuit monitors V_DD and keeps RESET output active as long as V_DD remains below the threshold voltage V_IT . An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time starts after V_DD has risen above the threshold voltage V_IT.

When CT is connected to GND a fixed delay time of typical 10 ms is asserted. When connected to V_DD the delay time is typically 200 ms.

When the supply voltage drops below the threshold voltage V_IT, the output becomes active (low) again.