?

`include "timescale.v"

// synopsys translate_on

`include "can_defines.v"

?

module can_top

(

? `ifdef CAN_WISHBONE_IF

??? wb_clk_i,

??? wb_rst_i,

??? wb_dat_i,

??? wb_dat_o,

??? wb_cyc_i,

??? wb_stb_i,

??? wb_we_i,

??? wb_adr_i,

??? wb_ack_o,

? `else

??? rst_i,

??? ale_i,

??? rd_i,

??? wr_i,

??? port_0_io,

? `endif

? cs_can_i,

? clk_i,

? rx_i,

? tx_o,

? irq_on,

? clkout_o

);

?

parameter Tp = 1;

?

`ifdef CAN_WISHBONE_IF

? input??????? wb_clk_i;

? input??????? wb_rst_i;

? input? [7:0] wb_dat_i;

? output [7:0] wb_dat_o;

? input??????? wb_cyc_i;

? input??????? wb_stb_i;

? input??????? wb_we_i;

? input? [7:0] wb_adr_i;

? output?????? wb_ack_o;

?

? reg????????? wb_ack_o;

? reg????????? cs_sync1;

? reg????????? cs_sync2;

? reg????????? cs_sync3;

?

? reg????????? cs_ack1;

? reg????????? cs_ack2;

? reg????????? cs_ack3;

? reg????????? cs_sync_rst1;

? reg????????? cs_sync_rst2;

`else

? input??????? rst_i;

? input??????? ale_i;

? input???? ???rd_i;

? input??????? wr_i;

? inout? [7:0] port_0_io;

?

? reg??? [7:0] addr_latched;

? reg????????? wr_i_q;

? reg????????? rd_i_q;

`endif

?

input??????? cs_can_i;

input??????? clk_i;

input??????? rx_i;

output?????? tx_o;

output?????? irq_on;

output?????? clkout_o;

?

reg????????? data_out_fifo_selected;

?

?

wire???????? irq_o;

wire?? [7:0] data_out_fifo;

wire?? [7:0] data_out_regs;

?

?

/* Mode register */

wire???????? reset_mode;

wire???????? listen_only_mode;

wire???????? acceptance_filter_mode;

wire???????? self_test_mode;

?

/* Command register */

wire???????? release_buffer;

wire???????? tx_request;

wire???????? abort_tx;

wire???????? self_rx_request;

wire???????? single_shot_transmission;

?

/* Arbitration Lost Capture Register */

wire???????? read_arbitration_lost_capture_reg;

?

/* Error Code Capture Register */

wire???????? read_error_code_capture_reg;

wire?? [7:0] error_capture_code;

?

/* Bus Timing 0 register */

wire?? [5:0] baud_r_presc;

wire?? [1:0] sync_jump_width;

?

/* Bus Timing 1 register */

wire?? [3:0] time_segment1;

wire?? [2:0] time_segment2;

wire???????? triple_sampling;

?

/* Error Warning Limit register */

wire?? [7:0] error_warning_limit;

?

/* Rx Error Counter register */

wire???????? we_rx_err_cnt;

?

/* Tx Error Counter register */

wire???????? we_tx_err_cnt;

?

/* Clock Divider register */

wire???????? extended_mode;

?

/* This section is for BASIC and EXTENDED mode */

/* Acceptance code register */

wire?? [7:0] acceptance_code_0;

?

/* Acceptance mask register */

wire?? [7:0] acceptance_mask_0;

/* End: This section is for BASIC and EXTENDED mode */

?

?

/* This section is for EXTENDED mode */

/* Acceptance code register */

wire?? [7:0] acceptance_code_1;

wire?? [7:0] acceptance_code_2;

wire?? [7:0] acceptance_code_3;

?

/* Acceptance mask register */

wire?? [7:0] acceptance_mask_1;

wire?? [7:0] acceptance_mask_2;

wire?? [7:0] acceptance_mask_3;

/* End: This section is for EXTENDED mode */

?

/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */

wire?? [7:0] tx_data_0;

wire?? [7:0] tx_data_1;

wire?? [7:0] tx_data_2;

wire?? [7:0] tx_data_3;

wire?? [7:0] tx_data_4;

wire?? [7:0] tx_data_5;

wire?? [7:0] tx_data_6;

wire?? [7:0] tx_data_7;

wire?? [7:0] tx_data_8;

wire?? [7:0] tx_data_9;

wire?? [7:0] tx_data_10;

wire?? [7:0] tx_data_11;

wire?? [7:0] tx_data_12;

/* End: Tx data registers */