本文介紹了基于靜止圖像壓縮標(biāo)準(zhǔn)JPEG 基本模式的編碼器軟IP 核的設(shè)計(jì)與實(shí)現(xiàn)。本設(shè)計(jì)采用適于VLSI 實(shí)現(xiàn)的DCT 算法結(jié)構(gòu),單周期實(shí)現(xiàn)Huffman 編碼,圖像壓縮過(guò)程流水線(xiàn) 實(shí)現(xiàn), 達(dá)到高處理速率和高數(shù)據(jù)吞吐率。使用Design Compiler 在SMIC 0.18um CMOS 單元 庫(kù)下綜合，時(shí)鐘頻率可以達(dá)到125MHz，可處理每秒三十幀的1280*1024 SXGA 圖像。本IP 核可以方便地集成到諸如數(shù)碼相機(jī)、手機(jī)以及掃描儀等各種應(yīng)用中。
關(guān)鍵詞： JPEG; IP 核; ASIC; 流水線(xiàn)設(shè)計(jì);
Abstract：The paper presents the design and implementation of a soft encoder IP based on the JPEG baseline image compression standard. The design adopted the DCT algorithm architecture which is efficient for VLSI implementation and could encode the Huffman code in a clock period, compress the image in pipelining and obtain high speed and throughput. Synthesized in Design Compiler with the SMIC 0.18um CMOS library , the result is up to 125MHZ frequency and could handle 30 frames per second of 1280*1024 SXGA images. This IP can be conveniently integrated into various application such as digital camera、cell phone、and color FAX, etc.
Key words：JPEG; IP Core; ASIC; Pipelining Desig